1. Field of the Invention
The present invention generally relates to high density, high speed transistor memory chip packaging and more particularly, to a card structure containing within itself a three dimensional configuration of memory chips.
2. Description of the Related Art
High speed signal transmission between computer system components is becoming increasingly important as machine cycle times are pushed toward ever shorter values. Excessive lead lengths between circuit units introduces high lead inductance which impacts data transmission speed. In the case of conventional semiconductor memory packaging, for example, memory chips are placed in memory modules which, in turn, are mounted on memory cards. Such three-level packaging introduces signal path length delays which are likely to become unacceptable in upcoming high speed machines. To take full advantage of the high speed signals generated at the chip level, the chip input-output (I/O) pad to card structure signal line distance must be made as short as possible.
In U.S. Pat. No. 4,849,284, issued on Jul. 18, 1989 to David J. Arthur et al. for Electric Substrate Material, a ceramic filled fluoropolymer-based electrical substrate material is proposed for forming printed wiring boards for surface-mounted integrated circuit chips. The substrate material is said to enable board characteristics including low signal propagation delay. Increased chip density at the board level is not addressed, however.
U.S. Pat. No. 4,635,356, issued on Jan. 13, 1987 to Masayuki Ohuchi et al. for Method of Manufacturing A Circuit Module discloses a method for potting discrete resistors, capacitors and transistor devices into a multilayered module configuration. The supporting module structure for the potted devices is the cured potting resin itself. Although the described technique provides some measure of increased discrete device density, the materials used and the resulting structure are not aimed at solving the aforementioned problem of high density, high speed transistor memory chip packaging and its impact on high speed machine cycle time.